1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a calibration circuit connected to a calibration terminal or pad (ZQ). In this connection, the calibration circuit may be often called a ZQ calibration circuit in the instant specification.
2. Description of the Related Art
A semiconductor device (DRAM) called DDR3 is equipped with a ZQ calibration circuit which automatically adjusts an impedance of an output buffer of the device. FIG. 8 shows an example of a ZQ calibration circuit.
As shown in FIG. 8, a pull-up driver 802 and a pull-down driver 803 are connected to a DQ pad 801 within a chip. The ZQ calibration circuit serves to adjust output impedances of the pull-up driver 802 and the pull-down driver 803 by making use of an external resistance (240[Ω]) 805 which is connected to a ZQ pad 804 outside of the chip.
An ordinary ZQ calibration method employs a two-step adjustment method of first adjusting a pull-up (Pch) side, i.e., the pull-up driver 802 and then adjusting a pull-down (Nch) side, i.e., the pull-down driver 803.
Specifically, to adjust the Pch-side first, a Pch-side comparator 808 compares an output of a first Pch-side DQ replica 806 connected to the external resistance 805 through the ZQ pad 804 with an output (VDD/2[V]) of a Pch-side VDD/2 generation circuit 807.
A ZQ control circuit (namely, a calibration control circuit) 809 generates a Pch-replica code in response to an output of the Pch-side comparator 808 so that an output of the first Pch-side DQ replica 806 becomes equal to VDD/2[V]. A Pch-side replica control circuit 810 controls output impedances of the first Pch-side DQ replica 806 (and a second Pch-side DQ replica 811) according to the Pch-replica code.
When the output of the first Pch-side DQ replica 806 becomes equal to VDD/2[V] by repeating the above operation, the ZQ control circuit 809 determines or judges that the output impedance of the first Pch-side DQ replica 806 becomes equal to the external resistance 240[Ω] and generates a Pch-DQ code to put a state of the pull-up driver 802 into the same state of the first Pch-side DQ replica 806. With this operation, an output impedance of the pull-up driver 802 is set to 240[Ω] which is equal to the external resistance 805.
Next, adjustment of an Nch-side is performed. An output impedance of the second Pch-side DQ replica 811 is set to 240[Ω] by the adjustment operation on the Pch-side described above. An Nch-side comparator 814 compares an output of an Nch-side DQ replica 812 connected to the second Pch-side DQ replica 811 with an output of an Nch-side VDD/2 generation circuit 813. The ZQ control circuit 809 generates an Nch-replica code according to an output of the Nch-side comparator 814.
An Nch-side replica control circuit 815 adjusts an output impedance of the Nch-side DQ replica 812 according to the Nch-replica code. When the output of the Nch-side DQ replica 812 becomes equal to the output of the Nch-side VDD/2 generation circuit 813 by repeating the above operation, the ZQ control circuit 809 generates an Nch-DQ code to put a state of the pull-down driver 803 into the same state of the Nch-side DQ replica 812.
With the above operation, the output impedances of the pull-up driver 802 and the pull-down driver 803 are adjusted to the same value as that of the external resistance 805.
JEDEC (Joint Electron Devices Engineering Council) prescribes, as ZQ calibration commands, two types of calibration commands, i.e., a ZQCL (init, oper) (namely, ZQ Calibration Long) command and a ZQCS (ZQ calibration short) command.
The ZQCL command is a calibration command that is input when a DRAM is not accessed for a long period of time after a power is supplied and after a self refresh is performed and the like. As a result, a temperature and a voltage are varied when the ZQCL command is issued. Responsive to the ZQCL command, ZQ calibration is performed within a period of 512 tCK (init) or within a period of 256 tCK period (oper).
On the other hand, the ZQCS command is a calibration command that is periodically input (for example, each 128 ms) while the DRAM is ordinarily accessed. Responsive to the ZQCS command, the ZQ calibration is performed within a period of 64 tCK.
In the ZQ calibration, a certain predetermined time is needed to make a comparator compare voltages and to change impedance of a DQ replica buffer within a calibration operation. This shows that, when a frequency of external clocks becomes higher, it becomes difficult to adjust impedance each time the external clocks are activated. To cope with the above problem, the ZQ calibration usually controls impedance by the use of internal clocks obtained by dividing the external clocks.
FIG. 9 exemplifies the ZQ control circuit 809 which is illustrated in FIG. 8 and which has a divider circuit, namely, a frequency divider circuit.
The ZQ control circuit (calibration control circuit) 809 of FIG. 9 has the divider circuit 901, a B/E counter 902, a command latch circuit 903, a Pch-side hit determination circuit 904, a Pch-side mask circuit 905, a Pch-side AND circuit 906, a Pch-side up/down counter circuit 907, a Pch-side initial code storage unit 908, and first and second latch circuits 909, 910.
The illustrated ZQ control circuit 809 further has an Nch-side hit determination circuit 911, an Nch-side mask circuit 912, an Nch-side AND circuit 913, an Nch-side up/down counter circuit 914, an Nch-side initial code storage unit 915, and a third latch circuit 916.
Now, the ZQ control circuit 809 illustrated in FIG. 9 is given the input commands (cmd), such as ZQCL, ZQCS, the external clocks CK, and pull-up and pull-down comparator signals output from the comparators 808 and 814. The ZQ control circuit 809 has a divider circuit 901 which divides external clocks CK into divided clocks in accordance with a predetermined division factor (for example, may be equal to 16) and supplies the divided clocks as update clocks CKL to the Pch- and Nch-side hit determination circuits 904, 911, the mask circuits 905, 912, and the up/down counter circuits 907, 914. Thus, the ZQ control circuit 809 of FIG. 9 is operated in a single sequence of the update clocks CLK given as its basic clocks.
As described above, in the ZQ control circuit 809 of FIG. 9, the single sequence of the update clocks CLK is supplied to both the Pch- and Nch-side circuits. Therefore, it is also possible to share a single up/down counter on the pull-up and pull-down sides. In this case, the area occupied by the ZQ control circuit 809 can be reduced.
Next, an operation of the ZQ control circuit 809 will be explained with reference to FIG. 10 in addition to FIG. 9. Herein, FIG. 10 is a signal waveform diagram of various portions of the ZQ control circuit 809 illustrated in FIG. 9.
The divider circuit 901 generates the update clocks CLK by dividing the external clocks CK in the above-mentioned manner.
The B/E counter 902 counts the external clocks CK of the number (512, 256 or 64 tCK) prescribed according to an input command cmd and notifies the command latch circuit 903 of an end of count (end of ZQ calibration).
The command latch circuit 903 outputs Pch-enable signals or Nch-enable signals in response to the input command cmd (ZQCL or ZQCS) and stops an output thereof in response to a notification from the B/E counter 202.
In FIG. 10, the division factor of the divider circuit 901 is set to 16. Herein, it is assumed that the ZQCS command is input as the input command cmd and the Pch-enable signals are output from the command latch circuit 903. Further, it is assumed in FIG. 10 that an initial code #05 is stored in the initial code memory units 908 and 915.
Responsive to the ZQCS command, the command latch circuit 903 outputs the Pch-enable signals. Since a calibration period performed by the ZQCS command is prescribed as 64 tCK, as mentioned above, the Pch-enable signals are set to a high level only during a 64/16=4 [=update clock period].
When the Pch-enable signals are set to the high level, the Pch-side up/down counter 907 captures the initial code #5 stored in the Pch-side initial code storage unit 908 at the time a next update clock CLK rises. With this operation, an output D of the Pch-side up/down counter 907 is set to #05.
Thereafter, each time an update clock CLK rises, the Pch-side up/down counter 907 increases or decreases a count value according to an output E from the Pch-side hit determination circuit 904. With this operation, an output of the Pch-side up/down counter 907 changes from #05 to #08 through #06 and #07.
The Pch-side hit determination circuit 904 determines or judges a hit based on the comparator signal output from the Pch-side comparator (808 of FIG. 8). FIG. 10 shows the case where no “hit” is judged or detected within each high level period of the Pch enable signals. In this event, the first and the second latch circuits 909 and 910 latch the output D=#07 of the Pch-side up/down counter circuit 907 that appears at a time when the Pch-enable signals are changed to the low level.
In the illustrated example, it is to be noted that an effective update number of times (=a number of adjustment steps) of the Pch-side up/down counter circuit 907 is equal to two and that the adjustment steps are performed two times within second and third ones of the update clocks CLK during a calibration period (in 64/16=4).
The outputs D latched by the first and second latch circuits 909 and 910 are output to the outside as the Pch-replica code and the Pch-DQ code, respectively. Further, the Pch-DQ code is stored in the initial code storage unit 908 as a new initial code.
FIG. 11 shows a waveform of operation performed when judgment of “hit” is made in the Pch-side hit determination circuit 904 (FIG. 9) during the high level period of the Pch-enable signals.
When a pulse signal PHIT, representative of “hit”, is output from the Pch-side hit determination circuit 904, the pulse signal is supplied as an output C from the Pch-side AND circuit 906 to the B/E counter 902. As a result, the B/E counter 902 stops counting the external clocks CK and notifies the command latch circuit 903 of the count stop.
On receiving the notification of the count stop from the B/E counter 902, the command latch circuit 903 changes the Pch-enable signals to the low level, as shown in FIG. 11. In response to the low level of the Pch-enable signals, an output D=#06 from the Pch-side up/down counter circuit 907 is latched by the first and second latch circuits 909 and 910. Thus, in this case, a period of the high level of the Pch-enable signals becomes shorter than 64 tCK.
The Nch-replica code and the Nch-DQ code in the Nch-side are also generated in a manner similar to the above-mentioned case.
As readily understood from FIGS. 10 and 11, the Pch-side up/down counter circuit 907 continues count-up or count-down, regardless of whether or not the ZQ calibration is performed, that is, regardless of whether or not the Pch-enable signals are set to the high level by the command latch 903. The Pch-side hit determination circuit 904 also receives an input of the comparator signals in timed relation with the update clocks CLK and determines a hit regardless of whether or not the Pch-enable signals are set to the high level. Accordingly, there is a possibility that the Pch-side hit determination circuit 904 also wrongly outputs a pulse signal PFALSE representative of detection of hit at a rise time of the first one of the update clocks CLK after the Pch-enable signals are changed to the high level, as illustrated in FIG. 11.
When such a pulse signal PFALSE is input to the B/E counter circuit 902, the Pch-enable signals are changed to the low level, and the ZQ calibration period is finished without practically executing any ZQ calibration operation.
To cope with the above problem, the Pch-side mask circuit 905 outputs a mask signal as an output B during a period in which the pulse signal PFALSE might appear at the start of calibration. The mask signal B is supplied to the Pch-side AND circuit 906 which serves to mask the pulse signal PFALSE.
Thus, since the pulse signal PFALSE is not supplied to the B/E counter circuit 902, the ZQ calibration can be normally started.
On the Nch-side, the pulse signal PFALSE is also output from the Nch-side hit determination circuit 911 for the first time and shows determination of hit. Like in the Pch-side, the pulse signal PFALSE can be prevented from being input to the B/E counter circuit 902 by using the Nch-side mask circuit 912 and the AND circuit 913 after the Nch-enable signal is changed to the high level.
Furthermore, the ZQ calibration period based on the ZQCL command is made longer than the ZQ calibration period based on the ZQCS command as described above. Accordingly, when, for example, the ZQCL command is input, it might be considered to perform a control operation such that the Nch-sides are continuously adjusted after adjustment of the Pch-side.
Referring to FIG. 12, description will be made about an operation of the ZQ control circuit 809, which is performed in response to a ZQCLinit command. In this event, the Nch-side is assumed to be continuously adjusted after the Pch-side is adjusted. Calibration operations on the Pch-side and the Nch-side are the same as that described above. Therefore, description will be mainly made about switching the calibration operation on the Pch-side to the calibration operation on the Nch-side.
When the ZQCL command is input, the Pch-side calibration is performed like in the above-mentioned manner.
When the Pch-side hit determination circuit 904 outputs a pulse signal PHIT representative of detection of hit in the form of one shot pulse, the pulse signal PHIT is given to the B/E counter 902 as the output C through the Pch-side AND circuit 906. On receiving the pulse signal PHIT, the B/E counter 902 initializes a count value and supplies an output Z to the command latch circuit 903. In response to the output Z from the B/E counter 902, the command latch circuit 903 falls down the Pch-enable signal and raises up the Nch-enable signal. Thereafter, the calibration on the pull-down side is performed like in the above-mentioned manner.
When the ZQCL command is executed, the number of clocks which can be used for an adjustment step during the calibration period (the number of all the update clocks 32 (=512/16)) is equal to 28.
As described above, the ZQ control circuit 809 illustrated in FIG. 9 performs calibration in response to the input command.
In the ZQ control circuit 809 described above, the up/down counter circuits, such as 907, 914 are always operated not only for the calibration period but also for a period except the calibration period.
Alternatively, proposal has been also made about a calibration circuit in which up/down counters are operated only when calibration is performed (for example, refer to Japanese Unexamined Patent Application Publication No. 2008-48361). In this event, the up/down counters are stopped except the duration of calibration.
A calibration period is prescribed by the number of external clocks. Accordingly, when the speed or frequency of the external clocks is increased, the calibration period becomes short in dependency upon the speed of the external clocks. Under the circumstances, a limited number of update clocks must be effectively used.
In the above-mentioned ZQ control circuit 809, since an initial code must be sent to the up/down counter at the start of calibration, update clocks are required to fetch each initial code. This structure brings about a problem that the update clocks should be used for fetching the initial code and, as a result, the update pulses usable for an adjustment step are reduced in number.
Further, when calibration starts, the above-mentioned ZQ control circuit masks signals output from the hit determination circuit. However, when the speed of the external clocks is increased, a plurality of update clocks (for example, two update clocks) may be masked. This shows that the number of update clocks which can be used for an adjustment step is also reduced
Further, in the above-mentioned ZQ control circuit, it is assumed that calibration is performed in response to the ZQCL command. In this case, an operation for setting the Nch-enable signal to the high level must be performed within a single update clock after the hit signal is output from the Pch-side, in consideration of the number of adjustment steps. However, since the update clocks are not synchronized with the Pch- and Nch-enable signals, there is a problem in that a timing margin is made severe due to the existence of timing skew. When the Nch-enable signals are more delayed than a next update clock, a problem arises in that the number of the update clocks which can be used to the adjustment step is further reduced by one.
Further, since the calibration circuit disclosed in Japanese Unexamined Patent Application Publication No. 2008-48361 has no hit determination circuit (different from FIG. 9), the operation clocks of the up/down counter circuit are stopped by a calibration command issued from the outside or by set signals and reset signals based on the calibration command. Accordingly, even when an impedance adjustment of an output buffer is finished within a predetermined period, there is a possibility that power consumption increases because the up/down counter must be continuously operated until a predetermined period lapses.
Further, the calibration circuit disclosed in Japanese Unexamined Patent Application Publication No. 2008-48361 has such a structure that Pch-side calibration shifts to Nch-side calibration in response to reset signals which are activated based on that a half of a calibration period lapses when long calibration is performed based on the ZQCL command. Accordingly, even if the Pch-side calibration is finished before the half of the calibration period lapses, there is a possibility that the Pch-side calibration cannot be shifted to Nch-side calibration until the half of the calibration period lapses.
The present invention seeks to solve one or more of the above-mentioned problems by increasing a number of update clocks that can be used for an adjustment step during a calibration period.
The present invention seeks to solve one or more of the problems by stopping an operation of an up/down counter in response to completion of an impedance adjustment of an output buffer, even before calibration period lapses.